The two performance specifications that predominantly limit the current efficiency of low drop-out regulators are maximum load-current and transient output voltage variation requirements. Typically, more quiescent current flow is necessary for improved performance in these areas.
As the maximum load-current specification increases, the size of the pass device necessarily increases. Consequently, the amplifier's load capacitance, Cpar in Figure 1, increases. This affects the circuit's frequency performance by reducing the value of the parasitic pole present at the output of the amplifier [9]. Therefore, phase-margin degrades and stability may be compromised unless the output impedance of the amplifier is reduced accordingly.
As a result, more current in the buffer stage of the amplifier is required, be it a voltage follower or a more complicated circuit architecture. This is because the gate drive decreases as the input voltages decrease thereby demanding larger MOS pass elements to drive high output currents.
Further limits to low quiescent current arise from the transient requirements of the regulator, namely, the permissible output voltage variation in response to a maximum load- current step swing. The output voltage variation is determined by the response time of the circuit, the specified load-current, and the output capacitor [9].
The worst-case response time corresponds to the maximum output voltage variation. This time limitation is determined by the closed-loop bandwidth of the system and the output slew-rate current of the error amplifier [9]. Consequently, the quiescent current of the amplifier's gain stage is limited by a bandwidth minimum while the quiescent current of the amplifier's buffer stage is limited by the slew-rate current required to drive Cpar.
The operation revolves around sensing the output current of the regulator and feeding back a ratio of the current to the slew-rate limited node of the circuit. Transistor Mps sources a fraction of the current flowing through the output transistor Mpo.
During low load-current conditions, the current fed back Iboost is negligible thereby yielding high overall current efficiency and not aggravating battery life.
Consequently, the current through the emitter follower is simply Ibias when load-current is low. During high load-current conditions, the current through the emitter follower is increased by Iboost, which is no longer negligible. The resulting increase in quiescent current has an insignificant impact on current efficiency because the load-current is, at this point, much greater in magnitude. However, the increase in current in the buffer stage aids the circuit by pushing the parasitic pole associated with Cpar P3 to higher frequencies and by increasing the current available for slew-rate conditions.
Frequency Response: When the load-current is low, the magnitude of the system's dominant pole P1 , determined by the output capacitor and the output impedance of the pass device, is also low [10]. Consequently, the unity gain frequency UGF is at low frequencies when the load-current is low, which relaxes the requirement of the parasitic pole at the output of the error amplifier P3 to be approximately greater than or equal to the minimum unity gain frequency UGFmin.
As load-current increases, however, the dominant pole increases linearly and consequently so does the UGF. Since the dominant pole P1 increases faster than the gain decreases with load-current, the unity gain frequency increases as the load- current increases equations 2 and 4.
These consequential effects of load-current on frequency response are graphically illustrated in Figure 3. Therefore, the parasitic pole P3 is also required to increase with load-current, which is achieved by the load dependent boost current.
The circuit can be designed such that P3 increases at a faster rate than the UGF with respect to load-current. Thus, current efficiency can be maximized to accommodate the load dependent requirements of P3. If the load dependence of P3 is not incorporated into the circuit, then more current than necessary is used during low load-current conditions. The frequency response behavior was confirmed through simulations. Rincon-Mora and Allen 7 Transient Response: The circuit of Figure 2 exhibits the transient response illustrated in Figure 4 depicted as trace "a" where a maximum load-current step swing is applied to the load.
As a result, a slew-rate condition does not aptly describe the operation of the circuit at hand. During a load-current transition from zero to maximum value, the response time of the circuit is dominated by the bandwidth of the system and the transient response of the buffer stage.
In particular, the response time is composed of the time required for the amplifier to respond tamp , for the sense PMOS transistor Mps to start conducting current tMps-on , for the positive feedback circuit to latch up tlatch-up , and for the output PMOS device Mpo to conduct the load-current tMpo.
The composite buffer stage is essentially a localized positive feedback circuit. The system is stable because the positive feedback gain is less than one. Consequently, the circuit attempts to latch up until the output transistor is fully turned on; at which point, the error amplifier forces the circuit back into the linear region.
As a result, the performance tradeoffs between the slew-rate and the quiescent current requirements of typical LDOs are circumvented. Figure 4 illustrates the simulation results showing the effect of the presence of boost element Mps in the circuit shown in Figure 2 on the output voltage, for the same biasing conditions.
In this case, the load-current is stepped from zero to a maximum of 50 mA in 1 ns. It is observed that the output voltage variation is lower for the circuit implementing the current efficient buffer resulting from a reduction in response time. This does not come at the expense of additional quiescent current flow during zero load-current conditions.
Consequently, current efficiency and battery life are maximized. Current Boosting 3. As a result, the aspect ratio of the power transistor needs to be increased to provide acceptable levels of output current. However, the parasitic gate capacitance also increases as the size of the PMOS transistor increases.
This constitutes an increase in Cpar in Figure 1, which pulls the parasitic pole P3 down to lower frequencies. Consequently, the phase margin of the system is degraded and stability may be compromised. This presents to be a problem when working in a low quiescent current environment. This results in a reduction of threshold voltage, commonly referred as the bulk effect phenomenon.
Consequently, the threshold voltage decreases as Vsb increases thereby effectively increasing the gate drive of the power PMOS transistor pass device. Maximum Output Current: For comparative analysis, the maximum current can be observed at the region where the power PMOS device is in saturation, which corresponds to the non drop-out condition.
Maximum output current results when the gate drive is at its peak, which occurs when the source to gate voltage Vsg is equal to the input voltage Vin. On the other hand, if the source to bulk junction is forward biased by 0. As a result, the output current capability of a PMOS device can be significantly increased by simply forward biasing the source to bulk junction. For the same input voltage, the maximum output current capability is increased as Vsb is increased, in other words, the circuit stays in regulation for an increased load-current range.
At a forward biased junction voltage of 0. Rincon-Mora and Allen 10 Figure 6 illustrates a successful implementation of the technique in a low drop-out regulator. This concept could easily be extended to dc-dc converters. The forward biased junction is defined by the voltage drop across the schottky diode Ds.
This voltage drop has to be less than a base-emitter voltage to prevent the parasitic vertical PNP transistors of the power PMOS device Mpo from turning on and conducting significant ground current through the substrate via the well. The effects of the parasitic bipolar transistors are mitigated by placing a heavily doped buried layer underneath the well of the power PMOS transistor, if this layer is available.
Furthermore, the ability to shut off Mpo is not degraded since the forward bias voltage is a function of load-current. This is similar to the operation of the current efficient circuit of Figure 2. A low-voltage, low quiescent current, low drop-out regulator Abstract: The demand for low-voltage, low drop-out LDO regulators is increasing because of the growing demand for portable electronics, i.
LDO's are used coherently with dc-dc converters as well as standalone parts. In power supply systems, they are typically cascaded onto switching regulators to suppress noise and provide a low noise output.
The need for low voltage is innate to portable low power devices and corroborated by lower breakdown voltages resulting from reductions in feature size. Low quiescent current in a battery-operated system is an intrinsic performance parameter because it partially determines battery life.
This paper discusses some techniques that enable the practical realizations of low quiescent current LDO's at low voltages and in existing technologies.
Publication Type. More Filters. LDO voltage regulators compose a small subset of the power supply arena. Low-drop-out LDO voltage regulators are used in analog applications that generally require low noise and high accuracy power … Expand.
A fast-response low-dropout regulator based on power-efficient low-voltage buffer. A power-efficient low-voltage buffer is presented. The proposed buffer contains a low-frequency zero generation circuit to perform frequency compensation and a slew-rate enhancement SRE circuit to … Expand.
View 1 excerpt, cites background. A low voltage CMOS low drop-out voltage regulator. The requirement of low voltage devices is crucial for portable devices that require extensive computations in … Expand. Power management is necessary to reduce the standby power of portable electronics such as cellular phones, pagers, laptops, etc. A capacitor-less low drop-out voltage regulator with fast transient response.
The thrust is towards reducing the number of battery cells, … Expand. A sub-1V low dropout regulator with improved transient performance for low power digital systems. Engineering, Computer Science. Ultra-low quiescent regulator including precise reference and the Power-On-Reset circuit.
0コメント